The present subject matter relates generally to semiconductor device testing and, more particularly, to a method and apparatus for measuring performance of hierarchical test equipment.
Semiconductor die are normally formed in large quantities on wafers of semiconductor material, for example, silicon. After die are singulated from the wafers, they may be individually packaged in plastic or ceramic packages, for example. A lead frame may support the die for wire bonding and packaging and provide the lead system for the completed package. In one example, electrical circuitry formed on the die is coupled to bond pads on the die to facilitate interconnection of the electrical circuitry with the outside world. During the wire bonding and packaging process, each bond pad is electrically connected to the lead frame. An encapsulating material protects and insulates the die, and the die is mounted in a package having external pins for interconnecting the electrical circuitry on the die, via the wire bonds, to the outside world.
Packaged devices are typically inserted into sockets on automated test equipment to perform various functional and performance tests prior to delivery to a customer. Test equipment for devices, such as CPUs, has grown dramatically in complexity in recent years as the complexity of CPU designs has also increased dramatically. These new generations of test equipment, such as ATE, and HST (hybrid system level test) in TMP (test mark pack) manufacturing can have as many as 84 sockets (test heads) on a single machine that test asynchronously. A typical testing facility has multiple test tools, each having a plurality of sockets. For a given manufacturing entity, multiple facilities may be used.
Measuring the performance of testers is difficult given the hierarchical machine architectures and the asynchronicity of the testing. Due to the difficulty in monitoring, a manufacturing facility may procure additional testers when capacity needs cannot be met. This procurement is done instead of optimizing the performance of current testers in the facility through detailed analysis of overall equipment efficiency (OEE), resulting in the expenditure of substantial resources for additional test equipment.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.